International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Wide Load Range, High Current Accuracy Low Drop Out Regulator with Load Tracking Compensation and Dual Soft Start for Wireless Charging System |
|---|---|
| ABSTRACT | This study introduces a High Voltage Low Dropout (LDO) regulator featuring a dual soft-start mechanism and load tracking compensation technique for Wireless Power Transfer (WPT) systems. The LDO design efficiently handles a broad input voltage spectrum from 5.15V to 20V and maintains stable performance under fluctuating load conditions ranging from 1mA to 1A. A notable advancement in this design is the dual soft-start mechanism, which enhances startup stability by separately regulating the pass transistor gate and the error amplifier input. Additionally, the load tracking compensation technique optimizes phase margin across diverse load currents, enhancing transient response and output stability. The regulator incorporates a current-sensing circuit for instantaneous overcurrent protection, accommodating load currents between 100mA and 1A. An integrated charge pump expands the error amplifier's operational range, allowing high-voltage compatibility while running on a 5V supply. Utilizing a BCD process, the proposed circuit delivers high power efficiency and robust performance within a compact layout measuring 0.8814 mm². These design features contribute to enhanced reliability and efficiency in WPT systems. |
| AUTHOR | M. SAI JYOTHI, K. SAI RAJESH, G. SRIKANTH, B.T.S. MANI DEEP, N. NAGARAJU U.G. Student, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India Assistant Professor, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India |
| VOLUME | 182 |
| DOI | DOI: 10.15680/IJIRCCE.2026.1403131 |
| pdf/131_Wide Load Range, High Current Accuracy Low Drop Out Regulator with Load Tracking Compensation and Dual Soft Start for Wireless Charging System.pdf | |
| KEYWORDS | |
| References | 1. B. Jang, A. Hejazi, R. E. Rad, Y. M. Qaragoez, I. Ali, Y. Pu, K. C. Hwang, Y. Yang, and K.-Y. Lee, "A 15-W triple- mode wireless power transmitting unit with high system efficiency using integrated power amplifier and DC–DC converter," IEEE Trans. Ind. Electron., vol. 68, no. 10, pp. 9574–9585, Oct. 2021. 2. J. Tang, L. Zhao, and C. Huang, "A wireless hysteretic controlled wireless power transfer system with enhanced efficiency and dynamic response for bioimplants," IEEE J. Solid-State Circuits, vol. 58, no. 4, pp. 1160–1171, Apr. 2023. 3. T. Lu, K. A. A. Makinwa, and S. Du, "A single-stage dual-output regulating voltage doubler for wireless power transfer," IEEE J. Solid-State Circuits, vol. 59, no. 9, pp. 2922–2933, Sep. 2024. 4. F. U. Ahmed, Z. T. Sandhie, L. Ali, and M. H. Chowdhury, "A brief overview of on-chip voltage regulation in high- performance and high-density integrated circuits," IEEE Access, vol. 9, pp. 813–826, 2021. 5. D. Xu, Y. Zhang, X. Luo, Z. Li, and Q. Pan, "A 0.96–0.9-V fully integrated FVF LDO with two-stage cross-coupled error amplifier," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 70, no. 10, pp. 3757–3761, Oct. 2023. 6. S.-W. Kwon, K.-I. Do, J.-M. Lee, U.-Y. Seo, and Y.-S. Koo, "Design of high-robustness LDO regulator with floating SCR based ESD protection circuit using high gain buffer," IEEE Access, vol. 12, pp. 33555–33568, 2024. 7. G. Li, H. Qian, J. Guo, B. Mo, Y. Lu, and D. Chen, "Dual active-feedback frequency compensation for output- capacitorless LDO with transient and stability enhancement in 65-nm CMOS," IEEE Trans. Power Electron., vol. 35, no. 1, pp. 415–429, Jan. 2020. 8. X. Ming, J.-J. Kuang, X.-C. Gong, J. Zhang, Z. Wang, and B. Zhang, "An NMOS LDO with TM-MOS and dynamic clamp technique handling up to Sub-10-μs short-period load transient," IEEE J. Solid-State Circuits, vol. 59, no. 2, pp. 583–594, Feb. 2024. 9. L. Huang, P. Luo, C. Wang, and X. Zhou, "A high speed on-chip soft-start technique with high start-up stability for current-mode DC–DC converter," IEEE Access, vol. 7, pp. 27579–27585, 2019. 10. M. Al-Shyoukh and H. Lee, "A compact ramp-based soft-start circuit for voltage regulators," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 7, pp. 535–539, Jul. 2009. 11. J.-J. Chen, Y.-S. Hwang, J.-Y. Lin, and Y. Ku, "A dead-beat-controlled fast-transient-response buck converter with active pseudo-current-sensing techniques," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 27, no. 8, pp. 1751–1759, Aug. 2019. 12. M. Doreyatim, M. Akbari, M. Nazari, and S. Mahani, "A low-voltage gain boosting-based current mirror with high input/output dynamic range," Microelectron. J., vol. 90, pp. 88–95, Aug. 2019. 13. Y.-S. Hwang, J.-J. Chen, Y.-T. Ku, and J.-Y. Yang, "An improved optimum-damping current-mode buck converter with fast-transient response and small-transient voltage using new current sensing circuits," IEEE Trans. Ind. Electron., vol. 68, no. 10, pp. 9505–9514, Oct. 2021. 14. X. Lai, J. Zhao, and B. Wang, "A current-mode DC–DC buck converter with accurate current limit using multiplex PWM comparator," IEEE Trans. Ind. Electron., vol. 69, no. 12, pp. 12739–12749, Dec. 2022. 15. G. S. Kim, J. K. Park, G.-H. Ko, and D. Baek, "Capacitor-less low-dropout (LDO) regulator with 99.99% current efficiency using active feedforward and reverse nested Miller compensations," IEEE Access, vol. 7, pp. 98630– 98638, 2019. 16. S.-K. Kao, J.-J. Chen, and C.-H. Liao, "A multipath output-capacitor-less LDO regulator," IEEE Access, vol. 10 , pp. 27185–27196, 2022. 17. Y. Lu, T.-A. Yen, R. D. Nayak, S. Alevoor, B. Talele, S. Patil, K. Kunz, and B. Bakkaloglu, "A novel parallel feed forward current ripple rejection (PFFCRR) technique for high load current high PSRR nMOS LDOs," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 33, no. 3, pp. 651–661, Mar. 2025. |
