International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Standard Cell Design Using Cadence Virtuoso in GPDK 90nm CMOS Technology |
|---|---|
| ABSTRACT | Standard cells are the fundamental building blocks of modern VLSI design, enabling efficient implementation of complex digital circuits. With continuous scaling of CMOS technology, designing optimized standard cells with reduced power consumption, improved speed, and minimal area has become essential.Here presents the design and implementation of standard cells using Cadence Virtuoso in GPDK 90nm CMOS technology. The proposed work includes schematic design, layout implementation, and verification using Design Rule Check (DRC) and Layout Versus Schematic (LVS). Various logic cells such as inverter, NAND, NOR, XOR, multiplexer, and sequential circuits are designed and analyzed.The performance of these cells is evaluated in terms of power, delay, and area. The results demonstrate that the designed standard cells meet design constraints and are suitable for scalable VLSI system design. |
| AUTHOR | S. HARISH VENKATA MANIKANTA, K. VASU, P. TEJASWINI, P. MOHITHA, K. SOWMYA SRI U.G. Student, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India Assistant Professor, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India |
| VOLUME | 182 |
| DOI | DOI: 10.15680/IJIRCCE. 2026.1403121 |
| pdf/121_Standard Cell Design Using Cadence Virtuoso in GPDK 90nm CMOS Technology.pdf | |
| KEYWORDS | |
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