International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Implementation of 12-bit R-2R DAC using Cadence Virtuoso in GPDK 90nm CMOS Technology |
|---|---|
| ABSTRACT | An R-2R DAC utilizes less special esteem which is in contrast with to the binary weighed- input DAC. Continuous sampling and measuring of an analog signal occur over time. This project depends on R-2R Ladder for investing Low power utilization, no dynamic chip and Low DNL. The DAC is executed in a virtuoso device on 90 Nanometer CMOS Technology. The two stages in our projects seems to be Operational Amplifier and R-2R Ladder Digital to analog converters enable transmission of analog signals over digital signal processing chips. Two stages are involved in the OP-Amp, the first one being a differential amplifier. We use this Differential Amplifier to obtain high gain and second stage namely Common Source Amplifier. It increases Gain that leaded from the first stage and increases it Output swing. In our project, 12- Bit R-2R DAC is implemented using CADENCE 90nm tool. |
| AUTHOR | P. ENEESHA, N. AKASH BABU, S. DINESH, Y. LAVANYA CHARAN TEJA, CH. AMALA U.G. Student, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India Assistant Professor, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India |
| VOLUME | 182 |
| DOI | DOI: 10.15680/IJIRCCE. 2026.1403114 |
| pdf/114_Implementation of 12-bit R-2R DAC using Cadence Virtuoso in GPDK 90nm CMOS Technology.pdf | |
| KEYWORDS | |
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