International Journal of Innovative Research in Computer and Communication Engineering
ISSN Approved Journal | Impact factor: 8.771 | ESTD: 2013 | Follows UGC CARE Journal Norms and Guidelines
| Monthly, Peer-Reviewed, Refereed, Scholarly, Multidisciplinary and Open Access Journal | High Impact Factor 8.771 (Calculated by Google Scholar and Semantic Scholar | AI-Powered Research Tool | Indexing in all Major Database & Metadata, Citation Generator | Digital Object Identifier (DOI) |
| TITLE | Adaptive DVFS and Power-Gated VLSI Techniques for Energy-Efficient Wireless Sensor Node Design |
|---|---|
| ABSTRACT | This project proposes an adaptive, hardware-driven power management architecture to improve energy efficiency in modern VLSI systems. The design integrates Dynamic Voltage and Frequency Scaling (DVFS) with Power Gating at the Register Transfer Level (RTL), eliminating the latency associated with conventional software-controlled approaches. The system employs a Finite State Machine (FSM) to dynamically switch between three operating modes—Idle (Power Gated), Low Frequency (50 MHz), and High Frequency (100 MHz)—based on real-time workload conditions. This enables rapid response to workload variations within 2 clock cycles, ensuring high performance during active periods while minimizing power consumption during idle states. The proposed architecture achieves significant dynamic power reduction and effectively controls leakage power, making it suitable for deep submicron technologies. The design is fully synthesizable and scalable, providing a robust solution to the power challenges in advanced System-on-Chip (SoC) designs. |
| AUTHOR | T. NAGA MANIKANATA, G. SIVA SANKAR, K. MAHA LAKSHMI, S. RAJESWARI U.G. Student, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India Assistant Professor, Department of ECE, SVIET Engineering College, Nandamuru, Pedana, Andhra Pradesh, India |
| VOLUME | 182 |
| DOI | DOI: 10.15680/IJIRCCE. 2026.1403111 |
| pdf/111_Adaptive DVFS and Power-Gated VLSI Techniques for Energy-Efficient Wireless Sensor Node Design.pdf | |
| KEYWORDS | |
| References | [1] D. Brooks et al., “Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors,” IEEE Micro, vol. 20, no. 6, pp. 26-44, 2000. [2] T. Burd and R. Brodersen, “Design issues for dynamic voltage scaling,” ISLPED, 2000. [3] K. Roy et al., “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” Proceedings of the IEEE, vol. 91, no. 2, 2003. [4] IEEE Std 1801-2018, “IEEE Standard for Design and Verification of Low Power Integrated Circuits (UPF),” IEEE, 2018. [5] Synopsys Inc., “Low Power Methodology Manual including UPF,” Synopsys Press, 2012. [6] S. Keating, “The Universal Verification Methodology (UVM) Class Reference,” Mentor Graphics, 2011. [7] J. Rabaey, “Digital Integrated Circuits: A Design Perspective,” Prentice Hall, 2nd Edition. |
